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Jason Ware

Over 20 years in digital design, synthesis and customer support.

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Equivalence Checking Today For a Smooth Tapeout Later
When do you get ready for tapeout? Two weeks before? One month before? Or are you proactive and realize that logic equivalence verification for tapeout should start as soon as the project starts? If I had a dollar for every time a customer called with   Read More »
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The Science of Synthesis
I am passionate about synthesis. Almost 20 years ago I began using Synopsys "Logic Compiler" to do combinational synthesis and optimization from Verilog RTL. At that time it did not support sequential constructs so Flip-Flops had to be manually   Read More »
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Changes to Cadence RTL Compiler PLE Mode with 8.1 release
RC-Physical has two major components to it: PLE (Physical Layout Estimate) which is a model to better represent physical capacitance during optimization; and Synth -to_placed which runs a full placement, trial route and optimization. This change affects   Read More »
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