Differentiation Through Hardware is Not Going Away
By
Jack Erickson
on
March 5, 2012
Last week at DVCon there was a panel discussion called "The Resurgence of Chip Design," which Richard Goering summarizes very well in his blog post "Will Differentiation Through Software Kill Chip Design?" The short answer is that
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TLM: The Year in Review, and Trends for 2012
By
Jack Erickson
on
January 2, 2012
2011 was my first full year in the land of Transaction-Level Modeling (TLM) design and verification, after spending my entire career to that point in RTL. I made my move upward in abstraction level in mid-2010 because it seemed like the time had finally
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High Level Synthesis for a Control-Dominated Design?
By
Jack Erickson
on
December 15, 2011
CDNLive! conferences are full of interesting and helpful presentations by customers as well as Cadence engineers. However, it's easy to miss good presentations due to the fact that tracks run in parallel, and also due to the fact that these conferences
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How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?
By
Jack Erickson
on
November 22, 2011
During the planning phase for SoC designs, teams have to choose whether to "make or buy" the pieces of IP that will compose the SoC. The drivers of this decision are well-chronicled in a recent article by Ann Steffora Mutchler, appropriately
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17M Gates in 8 Months with 2 Designers -- What is Your ROI for Higher-Abstraction Design and Verification?
By
Jack Erickson
on
October 4, 2011
In their presentation at the recent SystemC Japan conference, Renesas Micro Systems, Inc. (RMS) stated 2 SystemC "beginners" completed a 17M gate design in 8 months, achieving first-pass timing closure at 650 MHz targeting 40nm. Two thoughts
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IP Cannot be an Efficient Abstraction Level Without SystemC!
By
Jack Erickson
on
August 12, 2011
EDN recently featured a lengthy article entitled " SOCs: IP is the new abstraction. Reusable IP, not system-level language, has become the new level of abstraction ." The point of view is that SoC design now is such a large undertaking that
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Panel Discussion: Applying High-Level Synthesis in an SoC Flow
By
Jack Erickson
on
May 16, 2011
Last Thursday, EETimes hosted a virtual System on Chip event focused on IP integration in SoCs. Even with IP re-use comprising a large percentage of new SoCs, new IP must also be developed in order to differentiate on the hardware side. With RTL containing
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System Development Suite - Connecting Software to Hardware Design and Verification
By
Jack Erickson
on
May 9, 2011
I've been at CDNLive! EMEA watching demos of the newly announced System Development suite, and it's mindblowing. I'm seeing good old ncsim running Android interactively on the Virtual System Platform. You open an app in the virtual Android
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De-Mystifying SystemC: What is TLM?
By
Jack Erickson
on
February 3, 2011
In my last post I briefly mentioned that when designing hardware with SystemC, you do not need to allocate logic to register boundaries. And I said that was a blog post for another day. The first step is to separate the core functionality of the block
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SystemC: It's Neither Complicated Nor Belligerent!
By
Jack Erickson
on
January 24, 2011
I was recently talking to a customer who was looking to move up in abstraction from RTL to SystemC for all the usual good reasons (increased verification productivity, broader micro-architecture exploration, easier re-use, etc). However he was concerned
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