New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF
By
Adam Sherer
on
May 7, 2013
On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release . Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE
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IBM and Cadence Collaboration Improves Verification Productivity
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Adam Sherer
on
February 13, 2013
Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through collaboration, IBM and Cadence identify, refine, and deploy
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Your First Low-power Verification Project - Webinar
By
Adam Sherer
on
October 11, 2012
So your team just specified its first design with power management circuits. The designers are telling you, its just a few power shut-off domains defined by CPF or UPF. The verification should be easy-peasy right? Wrong. Each domain has complete controls
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UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar
By
Adam Sherer
on
October 11, 2012
Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple
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Accellera Systems Initiative Releases UVM 1.1b for SystemVerilog
By
Adam Sherer
on
June 1, 2012
Accellera Systems Initiive released the UVM 1.1b on its website June 1 and announced it on the UVM World site here . Cadence is happy to see this latest release maintaining the APIs and backward compatability of the UVM while improving the quality and
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Where There's Smoke, There's fire in the Belly of an Aspiring Engineer
By
Adam Sherer
on
April 2, 2012
Humans learn with their hands and, it turns out, electrical engineers are humans. Most of us fondly recall "experiments" we did that made electrical engineering our destiny. But what of the current generation? Have apps deadened the EE in the
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Assertions Help Avoid Chip Melt
By
Adam Sherer
on
March 22, 2012
When asked why the use of assertions for low power is rising, I say “at 40nm and below, the chips are just going to melt.” Ann Steffora Mutschler, you quoted me perfectly in your “ Avoiding Chip Melt ” article! Assertions are just
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Gentlemen, Start Your Simulation Engines
By
Adam Sherer
on
February 22, 2012
As we outlined in our recent performance white paper , every verification team has the need for higher performance simulation. Of course, you can expect on-going innovation from Cadence R&D, but there are some things you can do to get more from your
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Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements
By
Adam Sherer
on
January 30, 2012
Its’ all about RTL simulation. I mean gates. I mean turn-around-time. Project-level productivity. Mixed-signal. Low-power. UVM. And. And. And. … And the reality is that advanced node SoCs are so complex that it is truly about all of these
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UVM: "Everything that Can be Invented Has Been Invented" Not True!
By
Adam Sherer
on
January 26, 2012
Much like Charles Duell's famous 1899 quote**, the notion that the Universal Verification Methodology ( UVM ) is the be-all and end-all of verification methodology is an urban legend. The new Advanced Verification Topics book dispells this myth with
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