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 Cadence Member: About Team FED 

Team FED   | 445 points
San Jose, CA
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Member since: February, 2009
View Team FED's web site
 
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Bio Team FED consists of some of Cadence's leading applications experts in Front-End Design, led by:

Kenneth Chang
Well-versed in all things chip planing, logic design, synthesis, and equivalence checking.

Diego Hammerschlag
Has deep thoughts that span from logical and physical synthesis to chip planning.

Andy Hughes
Makes Design for Test and ATPG interesting for logic designers.

Jack Marshall
RTL design and synthesis oracle.

Matt Rardon
The guru when it comes to helping logic designers get physical.

Jason Ware
The man to talk to when you want to talk about synthesis or equivalence checking.

Additionally, other associates may drop by and add to our blog as we see fit. Academic Background No profile info has been provided Organization Affiliations "No ma'am, we're Front-End Designers."

We are in no way associated with any branch of the Federal Government. Community Interests Logic Design
 Personal Interests Faster, smaller, cooler, and more verifiable chips.We also like Verilog jokes. Publications Website:  www.cadence.com/community/members/Team%20FED.aspx
Blog:  www.cadence.com/community/ld/
 		My Friends

How-to Plans for ECOs - Advice From Experts
by Team FED on October 15, 2009 6:00 AM

Automatically Identify, Fix, and Prevent Congestion With RTL Compiler Physical
by Team FED on August 11, 2009 8:30 AM

Do You Also Need to be a DFT, STA, Verification, Low-Power, and Library Expert? Not Anymore!
by Team FED on August 04, 2009 6:00 AM