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 UVC Source Synchronous Interface 

Last post Tue, Jul 29 2014 1:47 AM by StephenH. 1 replies.
Started by rlanier 25 Jun 2014 02:15 PM. Topic has 1 replies and 810 views
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  • Wed, Jun 25 2014 2:15 PM

    • rlanier
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    • Joined on Thu, Mar 1 2012
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    UVC Source Synchronous Interface Reply

    I am attempting to develop a UVC with a source synchronous interface. I need to be able to control the flow of clock and data to the DUT such that when requested, the clock and data are gated off (essentially, the interface is disabled).

    Controlling the flow of data is relatively straight-forward. Where I'm getting wrapped around the axel is with the clock. How can I drive the clock from the driver such that is can gated off/on?

    • Post Points: 20
  • Tue, Jul 29 2014 1:47 AM

    • StephenH
    • Top 25 Contributor
    • Joined on Tue, Sep 2 2008
    • Bristol, Avon
    • Posts 278
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    Re: UVC Source Synchronous Interface Reply
    It might be simplest to add an ancilliary clock enable signal to the UVC's interface so that you can have a free-running clock into the UVC to allow cycle-based delay timing. You'd then externally gate the clock in the test harness before it goes to the DUT.
    Steve Hobbs / Applications Engineer / Cadence Functional Verification
    • Post Points: 5
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Started by rlanier at 25 Jun 2014 02:15 PM. Topic has 1 replies.