Iam working on 28nm design using soc encounter with the following steps,
Placement -> prectsopt -> CTS -> postcts_opt for setup and hold -. routing -> postroute opt
1)Iam using padding for the flops at placement stage.
2) CTS done by using the CellHalo for clock buffers,
3) Routing is done using routeDesign command
Here, at routing stage Iam getting lot of DRCs around #6000 while routing the design, but when I do verifyGeometry with the default options Iam getting around 1000 DRCs. confusion with this number.
"routeDesign shows different DRC count than VerifyGeometry"
Iam using the following nanorouting settings for routing the design.
setNanoRouteMode -routeWithViaOnlyForStandardCellPin 1:2
setNanoRouteMode -routeWithViaInPin false
setNanoRouteMode -routeUseMultiCutViaEffort medium
setNanoRouteMode -drouteAutoStop false
Please give me suggestions/advises inorder to reduce the number of DRC count at routeDesign.
Is any switch should be added while routing the design with setNanoRoueMode?
FYI Iam using EDI 11.13V tool.
Waiting for response.