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 Regarding more DRCs at routing for 28nm designs using routeDesign command using encan advanced license 

Last post Sun, Jun 22 2014 4:55 AM by MGREDDY. 0 replies.
Started by MGREDDY 22 Jun 2014 04:55 AM. Topic has 0 replies and 634 views
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  • Sun, Jun 22 2014 4:55 AM

    • MGREDDY
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    • Joined on Mon, May 19 2014
    • Posts 1
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    Regarding more DRCs at routing for 28nm designs using routeDesign command using encan advanced license Reply

    Hi,

    Iam working on 28nm design using soc encounter with the following steps,

    Placement -> prectsopt -> CTS -> postcts_opt for setup and hold -. routing -> postroute opt

    1)Iam using padding for the flops at placement stage.

    2) CTS done by using the CellHalo for clock buffers,

    3) Routing is done using routeDesign command

    Here, at routing stage Iam getting lot of DRCs around #6000 while routing the design, but when I do verifyGeometry with the default options Iam getting around 1000 DRCs. confusion with this number. 

    "routeDesign shows different DRC count than VerifyGeometry" 

    Iam using the following nanorouting settings for routing the design. 

     setNanoRouteMode -routeWithViaOnlyForStandardCellPin 1:2

    setNanoRouteMode -routeWithViaInPin false
    setNanoRouteMode -routeUseMultiCutViaEffort medium
     setNanoRouteMode -drouteAutoStop false
    routeDesign
     
    Please give me suggestions/advises inorder to reduce the number of DRC count at routeDesign.
    Is any switch should be added while routing the design with setNanoRoueMode?
    FYI Iam using EDI 11.13V tool. 
     
    Thank you,
     
    Waiting for response. 
    • Post Points: 5
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Started by MGREDDY at 22 Jun 2014 04:55 AM. Topic has 0 replies.