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 Spectremdl and Verilog-A variable 

Last post Tue, Jun 3 2014 11:05 AM by dan9876. 0 replies.
Started by dan9876 03 Jun 2014 11:05 AM. Topic has 0 replies and 1887 views
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  • Tue, Jun 3 2014 11:05 AM

    • dan9876
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    • Joined on Tue, Jun 3 2014
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    • Points 5
    Spectremdl and Verilog-A variable Reply

    Is it possible to write a spectreMDL measurement based on a Verilog-A variable? The verilog-A variable is exported in the ADE waveform viewer. But when I try to run spectreMDL I get the error message that the parameter or terminal is not found in the specificed scope.

    I already have:

    scs file: 

    saveOptions options saveahdlvars=all

     mdl file

    export real meas1 = u1:myahdlvar  

     

    Thanks! 

     

    • Post Points: 5
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Started by dan9876 at 03 Jun 2014 11:05 AM. Topic has 0 replies.