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 VerilogA definitions from ADE-XL 

Last post Tue, Apr 29 2014 3:30 AM by daasboe. 0 replies.
Started by daasboe 29 Apr 2014 03:30 AM. Topic has 0 replies and 179 views
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  • Tue, Apr 29 2014 3:30 AM

    • daasboe
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    • Joined on Thu, Mar 7 2013
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    VerilogA definitions from ADE-XL Reply

    Hi,

    I would like to be able to make a VerilogA `define in Cadence ADE-XL environment. Is that possible to do? The reason for this is that I want to have the same VerilogA module and symbol, and change sequence depending on what simulation I am running (`include different files). Is there another way to do it?

    BR,
    Daniel 

    • Post Points: 5
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Started by daasboe at 29 Apr 2014 03:30 AM. Topic has 0 replies.