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 ViVA bus plot to full view plot 

Last post Thu, Apr 17 2014 1:42 PM by 34892. 0 replies.
Started by 34892 17 Apr 2014 01:42 PM. Topic has 0 replies and 1853 views
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  • Thu, Apr 17 2014 1:42 PM

    • 34892
    • Not Ranked
    • Joined on Thu, Apr 17 2014
    • Woburn, MA
    • Posts 6
    • Points 75
    ViVA bus plot to full view plot Reply

    Hi,

     I am new to Cadance ViVA and wanted some help. After simulating my ADC (which has some verilogA models and some transistor level blocks), I plotted the clock signal to check for jitter (via Eye diagram). But the plot looks like a plot of 'bus' signal/digital signal instead of full view analog signal. Although when I plot the output of a ring osc. (a separate test bench and simulation), the plot is in full view (not sure how to put it any better!).

     

    I don't want the ADC clock plot to appear as digital bus plot, but want a full view. What should I do? Any help will be highly apprecited.

     

    Thanks

    -3489 

    -Regards, 34892
    • Post Points: 5
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Started by 34892 at 17 Apr 2014 01:42 PM. Topic has 0 replies.