I am new to Cadance ViVA and wanted some help. After simulating my ADC (which has some verilogA models and some transistor level blocks), I plotted the clock signal to check for jitter (via Eye diagram). But the plot looks like a plot of 'bus' signal/digital signal instead of full view analog signal. Although when I plot the output of a ring osc. (a separate test bench and simulation), the plot is in full view (not sure how to put it any better!).
I don't want the ADC clock plot to appear as digital bus plot, but want a full view. What should I do? Any help will be highly apprecited.