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 veriloga module library association 

Last post Wed, Apr 9 2014 11:34 PM by Andrew Beckett. 1 replies.
Started by mystika 27 Mar 2014 03:59 AM. Topic has 1 replies and 775 views
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  • Thu, Mar 27 2014 3:59 AM

    • mystika
    • Not Ranked
    • Joined on Thu, Mar 27 2014
    • Posts 1
    • Points 20
    veriloga module library association Reply

    Hi guys,

    I created a module in veriloga instantiating other modules like the resistors and capacitors found in the ahdlLib

    cap #(.c(1)) Cx(x, gnd);

    res #(.r(1T)) Raux(x, gnd);

    res #(.r(Rofff)) Roff(aux, minus); 

    the structure says it is associated with the analogLib with the view symbol.

    Structure summary for module "test1"

        child          bound to (library view)

        --------------------------------------

        Cx             (analogLib - view symbol)

        Raux           (analogLib - view symbol)

        Roff           (analogLib - view symbol) 

    My question is how do I bind the components to the ahdlLib or custom modules for the resistor and capacitor because when I run simulation I get these errors:

    ERROR (SFE-23): "" 33: Cx is an instance of an undefined model cap.

    ERROR (SFE-23): "" 34: Raux is an instance of an undefined model res.

     ERROR (SFE-23): "" 35: Roff is an instance of an undefined model res. 

     Thanks 

    • Post Points: 20
  • Wed, Apr 9 2014 11:34 PM

    Re: veriloga module library association Reply

    Use "capacitor" and "resistor" instead so that you are binding to the primitive devices in the simulator.

    Regards,

    Andrew.

    • Post Points: 5
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Started by mystika at 27 Mar 2014 03:59 AM. Topic has 1 replies.