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 Code coverage exclusion case 

Last post Wed, Feb 19 2014 10:50 PM by Selvavinayak. 0 replies.
Started by Selvavinayak 19 Feb 2014 10:50 PM. Topic has 0 replies and 1326 views
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  • Wed, Feb 19 2014 10:50 PM

    • Selvavinayak
    • Not Ranked
    • Joined on Thu, May 10 2012
    • chennai, Tamil Nadu
    • Posts 11
    • Points 145
    Code coverage exclusion case Reply
    Code coverage has added an "all-false" bin for Verilog case statements that do not contain a "default" clause.

    How to exclude a  default statement in  case statement in  code coverage while we simulate in cadence?
    • Post Points: 5
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Started by Selvavinayak at 19 Feb 2014 10:50 PM. Topic has 0 replies.