Hi i'm having an issue where i'm running a VerilogAMS testbench, which can instantiate verilogams blocks or their schematic equivalents. The verilogams models have supply sensitivity statements on the IO pins, so that when running a purely verilogams flow, i have no issues. However when swapping one of the verilogams views for schematic, i get errors about supply sensitivity.
I'm not sure how to set the supply sensitivity attributes for schematic views, when i have a text based top level/testbench. I can provide more information if required.
Can anyone help or point me to some documentatio?
I have also cross posted here:
Any help would be greatly appreciated. Thanks.