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 VRM four lumped elements model for PDN simulation 

Last post Wed, Jan 15 2014 5:21 AM by Abuhajer. 0 replies.
Started by Abuhajer 15 Jan 2014 05:21 AM. Topic has 0 replies and 872 views
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  • Wed, Jan 15 2014 5:21 AM

    • Abuhajer
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    • Joined on Fri, Oct 18 2013
    • Posts 3
    • Points 30
    VRM four lumped elements model for PDN simulation Reply

     

    Hello,

    I am using DC/DC Module TPS62590 in my design. When I set the PDN analysis in Allegro, it requires slew indcance (Lsew), Flat Resistance (Rflat), Output inductance (Lout), Output Resistance (Ro). I was not able to get the info directly from the data sheet. 
    I referred "Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology": To calculate Lslew, I must know the maximum transient current dI and the total amount of time dt for the TPS62590 to ramp this transient current either up or down.
    My question is: How can I derive these values, dI and dt, from the datasheet or from transient model?

    Thanks and Regards,

    • Post Points: 5
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Started by Abuhajer at 15 Jan 2014 05:21 AM. Topic has 0 replies.