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 Parasitic extraction of standalone metal traces (IC6.1.5) 

Last post Tue, Jan 7 2014 5:41 AM by Andrew Beckett. 1 replies.
Started by Wes8 06 Jan 2014 02:11 PM. Topic has 1 replies and 1852 views
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  • Mon, Jan 6 2014 2:11 PM

    • Wes8
    • Not Ranked
    • Joined on Fri, Jun 7 2013
    • Posts 2
    • Points 40
    Parasitic extraction of standalone metal traces (IC6.1.5) Reply

    Hi,

    I have a layout view with multiple metal traces adjacent to one another that I want to simulate as an array of resistors/capacitors. Is there a way to obtain the exact resistance/capacitance of these metal traces through parasitic extraction?

    I'm assuming there has to be some sort of linking between the layout of these metal traces and a schematic view in order to run LVS followed by QRC parasitic extraction, but how do you instantiate a standalone metal trace as a resistor/capacitor in schematic view?

    Thanks in advanced for any suggestions.

    • Post Points: 20
  • Tue, Jan 7 2014 5:41 AM

    Re: Parasitic extraction of standalone metal traces (IC6.1.5) Reply

     If the layout view really only has just tracks, you would probably need to use some kind of "metal resistor" to break the track in two and then have a different pin on each end of the track. Often PDKs/rule decks have metal resistors formed by a marker over a metal track which creates a small resistor but has the benefit of splitting the wire into two nets - and consequently you can have a pin on each end then. You'd then be able to have a symbol (and schematic) corresponding to this and so could go through the normal LVS, QRC and parasitic resimulation flow.

    Kind Regards,

    Andrew.

    • Post Points: 5
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Started by Wes8 at 06 Jan 2014 02:11 PM. Topic has 1 replies.