Home > Community > Forums > Digital Implementation > How to detect the clock glitch ?

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 How to detect the clock glitch ? 

Last post Mon, Jan 6 2014 6:24 PM by phoenixson. 1 replies.
Started by phoenixson 01 Jan 2014 11:59 PM. Topic has 1 replies and 4841 views
Page 1 of 1 (2 items)
Sort Posts:
  • Wed, Jan 1 2014 11:59 PM

    • phoenixson
    • Not Ranked
    • Joined on Tue, Aug 12 2008
    • beijing, Beijing
    • Posts 10
    • Points 110
    How to detect the clock glitch ? Reply

    Hi,All 

    Now , there are two clock signal in the design, the two clocks and select signal are synchronous, but the phase between them is uncertain, then use the selecting signal 'SEL' to switch the two clock dynamically. So it is possible that some glitch will occur, I want to know how to detect or check the glitch in encouter timing system intead of functional verification ?

    just like this :

    CLK_MUX = SEL ? CLK_0 : CLK_1; 

     Thank You. 

    Just do it.
    Filed under:
    • Post Points: 5
  • Mon, Jan 6 2014 6:24 PM

    • phoenixson
    • Not Ranked
    • Joined on Tue, Aug 12 2008
    • beijing, Beijing
    • Posts 10
    • Points 110
    Re: How to detect the clock glitch ? Reply
    Does anyone know this ? In the design , it 's a potential problem, so I want to find the solution out.
    Just do it.
    • Post Points: 5
Page 1 of 1 (2 items)
Sort Posts:
Started by phoenixson at 01 Jan 2014 11:59 PM. Topic has 1 replies.