Home > Community > Forums > Functional Verification > Communication between Verilog BFM and C-Based Verification bench

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Communication between Verilog BFM and C-Based Verification bench 

Last post Mon, Jan 6 2014 5:05 AM by StephenH. 1 replies.
Started by Arun Nellur 21 Dec 2013 11:41 AM. Topic has 1 replies and 4734 views
Page 1 of 1 (2 items)
Sort Posts:
  • Sat, Dec 21 2013 11:41 AM

    Communication between Verilog BFM and C-Based Verification bench Reply

    Hi

    I have a SOC verification bench in C/ASM and integrated SV/Verilog based BFM/VIP. The system level tests are based on C/ASM.

    To carry out functional simulations, the C/ASM tests are compiled, linked at the binary data of instructions are read into the On-Chip Memory for execution.

    How can we enable the above environment where BFM(say its a master), waits for the system to reach to a point where system is ready and BFM(say its a master) can request data from/to the SOC?

    To say in a short words, how can we achieve effective handshake between Verilog/SV(BFM) - C/ASM environments.


    Could somebody please donate your ideas. 

     

    Thanks
    Arun

    • Post Points: 20
  • Mon, Jan 6 2014 5:05 AM

    • StephenH
    • Top 25 Contributor
    • Joined on Tue, Sep 2 2008
    • Bristol, Avon
    • Posts 278
    • Points 4,450
    Re: Communication between Verilog BFM and C-Based Verification bench Reply

    Assuming that your C/ASM is running on a CPU inside the SoC, a common techniqueis to have some GPIO ports on the SoC connected to "registers" in the testbench. Your BFM would be triggered by the data written into the registers when the C/ASM test wants to control the BFM. This is one of the approaches used by the Cadence VIPs for SoC-level, our VIP documentation refers to it as "virtual register interface".

    An alternative approach is to stub out the CPU and use a BFM instead. This BFM is driven by your test software which runs on the host workstation and talks via SV-DPI to the BFM.

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
    • Post Points: 5
Page 1 of 1 (2 items)
Sort Posts:
Started by Arun Nellur at 21 Dec 2013 11:41 AM. Topic has 1 replies.