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  One question about system verilog `__LINE__ define  

Last post Thu, Dec 12 2013 5:59 PM by monkeyking. 0 replies.
Started by monkeyking 12 Dec 2013 05:59 PM. Topic has 0 replies and 4992 views
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  • Thu, Dec 12 2013 5:59 PM

    • monkeyking
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    • Joined on Wed, Jul 10 2013
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    One question about system verilog `__LINE__ define Reply

     There is a compiler derective in system verilog -- `__LINE__, it will expands to the current input line number. But I find it will return current line number -1.

    For example, in below code(the left is line number):

    1 initial begin
    2 signal_a = 0;
    3 signal_b = 1;
    4 $display("current line is: %0d",`__LINE__);
    5 end

    When I run this code using ncsim, it will output:

    current line is: 3

    It's so strange, I think it should output "current line is: 4", because obviously this line number is 4, but not 3.

    Can somebody tell me why?
    Thanks a lot!

    • Post Points: 5
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Started by monkeyking at 12 Dec 2013 05:59 PM. Topic has 0 replies.