I am trying to add montecarlo mismatch into a verilogA model (delay variation) using IC6.1.5.
I read on several post to use a custom scs model file that includes the verilog file and has a STAT section to define parameter variations. (like this http://www.cadence.com/Community/forums/t/27475.aspx). I dont know how to go further. Is this method correct?
Like in this post i have a verilog file with parameters, and a model.scs file included in ADE.
I can't find out how to link a symbol to the model in the scs file. Can anyone help me with this? I tried just putting the scs file next to the verilog file buth no changes are made seen.