I see VDD VSS open violations for full chip boundary . I have done my powerplan correctly and specified all he global nets
but i still open vioaltion on the full chip boundary
I feel these has false vioaltions , please help me on this
verify connectivity summary
18 Problem(s) (ENCVFC-200): Special Wires: Pieces of the net are not connected together.
49 Problem(s) (ENCVFC-92): Pieces of the net are not connected together.
67 total info(s) created.
Thanks in Advvance