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 Systemverilog macros with variable number of inputs(equivalent of "e" expression inputs ) 

Last post Wed, Oct 16 2013 9:02 AM by pravintavagad. 0 replies.
Started by pravintavagad 16 Oct 2013 09:02 AM. Topic has 0 replies and 3752 views
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  • Wed, Oct 16 2013 9:02 AM

    • pravintavagad
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    Systemverilog macros with variable number of inputs(equivalent of "e" expression inputs ) Reply

    Hi,

    Is there any way to define systemverilog macro with variable number number of inputs? We can solve this problem in "e" using expression inputs. Is there any equivalent solution in systemverilog??

    Any help will be highly appreciated.

    Thanks,

     

    pravin 

    • Post Points: 5
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Started by pravintavagad at 16 Oct 2013 09:02 AM. Topic has 0 replies.