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 How can I transfer a integer variable from verilog to VHDL? 

Last post Wed, Sep 18 2013 4:52 AM by victorhan. 0 replies.
Started by victorhan 18 Sep 2013 04:52 AM. Topic has 0 replies and 2145 views
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  • Wed, Sep 18 2013 4:52 AM

    • victorhan
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    • Joined on Tue, Sep 17 2013
    • Posts 5
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    How can I transfer a integer variable from verilog to VHDL? Reply

    Hi Candence:

    How can I transfer a integer variable from verilog to VHDL?

    As the code shows bellow:

    tb_top is verilog module;

    vhdl_top and bellows are vhdl module.

    module tb_top;

    integer i;

    $nc_force("tb_top.vhdl_top:ocmem:memarry[i]" , #data[i]);

    endmodule

    The ERROR message is:

    expecting a integer index i.

    • Post Points: 5
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Started by victorhan at 18 Sep 2013 04:52 AM. Topic has 0 replies.