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 identify long min width custom layout routes 

Last post Fri, Sep 13 2013 2:47 AM by stuso. 0 replies.
Started by stuso 13 Sep 2013 02:47 AM. Topic has 0 replies and 297 views
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  • Fri, Sep 13 2013 2:47 AM

    • stuso
    • Top 100 Contributor
    • Joined on Mon, Nov 3 2008
    • Posts 77
    • Points 1,315
    identify long min width custom layout routes Reply

    Hi there, i am looking to write a Skill procedure to identify long logic routes with high Resistance.

    Purpose: to find nets that are too long and un-buffered. In our current process we know that min width routes over X microns distance will become succeptable to signal integrity issues.

    Here are some things to note or that i have been thinking of:

    • Perhaps its easier to run this skill on an extracted view so i don't have the issue of hierarchy (the nets in question will be over various levels of layout hierarchy)
    • Maybe i can identify "logic" nets as anything that hangs of devices below a given gate length
    • I could alos identify logic nets as anything with a route less than a given width ( we use set widths for logic routing, though of course that would rely upon the layout guys having adhered to that rule of thumb)
    • In the past i have used a diva DRC deck to find joined nets but i prefer not to be tied to diva/calibre/assura/pvs ...etc as that can change. For example a few years back i wrote a simple diva DRC to find nets less than a given width, merged them to one new layer if they were electrically connected and then got the total area of these new shape (if Area was > than a given X area i flagged it as a DRC error). Crude but effective i found.
    • I'd also like my skill code to visually highlight violating nets

    I think to begin with i shall look for a way to identy that bits of metal are connected by given via's, if anyone knows of such functions please let me know.

    Many thanks






    • Post Points: 5
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Started by stuso at 13 Sep 2013 02:47 AM. Topic has 0 replies.