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 Ports mismatch 

Last post Thu, Sep 19 2013 12:26 PM by Kari. 1 replies.
Started by Ridus 26 Aug 2013 02:28 AM. Topic has 1 replies and 545 views
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  • Mon, Aug 26 2013 2:28 AM

    • Ridus
    • Not Ranked
    • Joined on Thu, Jul 11 2013
    • Posts 2
    • Points 40
    Ports mismatch Reply

    Hi ,

     

    I am running LVS, I have assigned ports in the desing but still in LVS report layout has 0 ports. I am working on Encounter10.13

     dv_obj_count -transformed_nets {132639 59910} -transformed_inst {180591 116168} -transformed_port {0 423}

    dv_discrep 1 {Incorrect Nets}

     

    I am using the below command to save the netlist. 

    saveNetlist design.v -excludeLeafCell -includePowerGround -excludeLogicalCell {FILL16BWP FILL8BWP FILL4BWP FILL2BWP FILL1BWP} -includePhysicalCell {GDCAP4BWP GDCAP2BWP GDCAP3BWP GDCAP4BWPLVT GDCAP10BWP GDCAP3BWPLVT GFILL3BWP GFILL2BWP GFILL4BWP GFILL3BWPLVT GFILL2BWPLVT GFILL4BWPLVT GFILL10BWP} -replaceTieConnection

    Kindly help me on this.

    Thank you. 

    Regards.. 

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    • Post Points: 20
  • Thu, Sep 19 2013 12:26 PM

    • Kari
    • Top 10 Contributor
    • Joined on Tue, Jul 15 2008
    • Cary, NC
    • Posts 693
    • Points 14,155
    Re: Ports mismatch Reply
    if you think the problem is in the layout, it has nothing to do with your netlist. however, typically you want a physical verilog for LVS (saveNetlist -phys). Do you have an edtext file for your top-level ports that you include in the LVS run?
    • Post Points: 5
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Started by Ridus at 26 Aug 2013 02:28 AM. Topic has 1 replies.