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 Formal Verification with SystemVerilog and ifv 

Last post Wed, Jul 31 2013 3:43 PM by ckomar. 1 replies.
Started by m123 31 Jul 2013 04:35 AM. Topic has 1 replies and 484 views
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  • Wed, Jul 31 2013 4:35 AM

    • m123
    • Not Ranked
    • Joined on Wed, Jul 31 2013
    • Posts 1
    • Points 20
    Formal Verification with SystemVerilog and ifv Reply

    Hi,

    i am trying to verify some SystemVerilogAssertions of a SV implementated communication network with incisif formal verifier, but the verification process takes a very long time and the computer crashes after 20 hours. The assertions test the whole network of sending and receiving. So is it possible to reduce the duration with some special commands (i use auto_dist as engine) or is the complexity an almost unsolveable problem?

     

    • Post Points: 20
  • Wed, Jul 31 2013 3:43 PM

    • ckomar
    • Not Ranked
    • Joined on Thu, Jul 17 2008
    • Phoenix, AZ
    • Posts 11
    • Points 100
    Re: Formal Verification with SystemVerilog and ifv Reply

    Hi,

     Complexity can often be addressed with methodology and tool capabilities. But this is a large topic that will be difficult to discuss using this forum. I can suggest a couple of things

    1) view an older post in which document was posted on how to improve performance

    http://www.cadence.com/community/forums/T/26285.aspx 

    2) discuss with your local AE

     Thanks,

    Chris 

    • Post Points: 5
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Started by m123 at 31 Jul 2013 04:35 AM. Topic has 1 replies.