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 controlling the analog solver within verilog 

Last post Sat, Jul 20 2013 6:36 AM by freitas. 0 replies.
Started by freitas 20 Jul 2013 06:36 AM. Topic has 0 replies and 413 views
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  • Sat, Jul 20 2013 6:36 AM

    • freitas
    • Top 500 Contributor
    • Joined on Wed, Nov 23 2011
    • Posts 29
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    controlling the analog solver within verilog Reply

    Hello, 

    I read in some application note that, starting from 12.x, incisiv would support Verilog system tasks (i.e., $cds_analog_on and 

    $cds_analog_off) to control when the analog solver starts/stops.

     

    These tasks would simplify our verification environment.  Does anyone know if they are being supported? I can't find any reference to them in the documentation.

     

     Thanks in advance

     

     

     

    • Post Points: 5
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Started by freitas at 20 Jul 2013 06:36 AM. Topic has 0 replies.