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 Dynamic parameter and verilogA code 

Last post Fri, Jul 12 2013 1:57 AM by KMan11. 7 replies.
Started by KMan11 04 Jul 2013 10:57 AM. Topic has 7 replies and 1078 views
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  • Thu, Jul 4 2013 10:57 AM

    • KMan11
    • Not Ranked
    • Joined on Mon, Jun 10 2013
    • Bristol, Avon
    • Posts 8
    • Points 100
    Dynamic parameter and verilogA code Reply

    Hello

      I have a VerilogA block which reads in single binary bits from a file, on rising edges of an incoming clock (generated by VPULSE).

     I created a simple file where I have tscale and tscale_value and time and period values.

    The 'period' parameter, incidentally, changes the period of the incoming clock.

     I can simulate and I clearly see the period of the spectre VPULSE clock change by a factor 10 as desired.

    Yet the output of my VerilogA fails to output anything after this change in period.  My VerilogA block doesn't take this 'period' variable, and consists of the following after (parameter, real, pin declarations (electrical))

    analog begin

    @(initial_step)
    fid=$fopen(type,"r");


     @ (cross( V(Mclk) - vtrans_clk, +1 ))
     begin

     $fscanf(fid,"%d",int_cs[0]);
     end

    vout_val = int_cs[0] * vdd;

    V(cs0) <+ 1*transition(vout_val, tdel, trise, tfall);
    end

    endmodule  

     

    Does anyone know whether changing the clock period (by a factor 10), without changing reltol would result in a lack of output from the verilogA block, yet the incoming clock changes correctly. I've tried changing the clock by multiplying and dividing by 10 from the initial period, but to no avail.

     

    K

     

    • Post Points: 20
  • Mon, Jul 8 2013 5:22 AM

    Re: Dynamic parameter and verilogA code Reply

    Not entirely obvious what your problem is from your description, so I tried creating this example, based around your VerilogA code snippet.

    First here's the VerilogA code I used:

    `include "disciplines.vams"

    module dynparam (Mclk,cs0);
    input Mclk;
    output cs0;
    electrical Mclk,cs0;

    parameter vtrans_clk=0.5;
    parameter type="dynparam.vals";
    parameter vdd=1.5;
    parameter tdel=0;
    parameter trise=1n;
    parameter tfall=1n;

    integer int_cs[10:0];
    real vout_val;
    integer fid;

    analog begin

    @(initial_step)
    fid=$fopen(type,"r");


     @ (cross( V(Mclk) - vtrans_clk, +1 ))
     begin

     $fscanf(fid,"%d",int_cs[0]);

     end

    vout_val = int_cs[0] * vdd;

    V(cs0) <+ 1*transition(vout_val, tdel, trise, tfall);
    end

    endmodule 

    Next here's the dynparam.vals file referenced (the sequence of "bits" (I made the numbers other than 1 and 0 just to make it stand out a bit more):

     1
    2
    0
    -1
    3
    4
    2
    0
    1
    3
    4
    2
    0
    1

    And then here's my netlist - I'm using the transient analysis's dynamic parameter capability with a paramset to vary the period (I wasn't sure how you were varying the period of the pulse):

     //

    parameters period=100n tr=1n
    I1 (clk op) dynparam
    Vclk (clk 0) vsource type=pulse period=period width=period/2 val0=0 val1=1 rise=tr fall=tr

    ahdl_include "dynparam.va"

    dyntable paramset {
    time period
    0 100n
    350n 1u
    }

    tran tran stop=10u paramset=dyntable

    This worked perfectly - see the attached graph. If this doesn't match what you're trying to do, you'll need to provide some more detail...

    Regards,

    Andrew


    • Post Points: 35
  • Mon, Jul 8 2013 8:10 AM

    • KMan11
    • Not Ranked
    • Joined on Mon, Jun 10 2013
    • Bristol, Avon
    • Posts 8
    • Points 100
    Re: Dynamic parameter and verilogA code Reply
     Hi Andrew,

    So I bundled your code into 2 files : test.scs containing the instantiation and dynparam.va as you have it and simulated at the UNIX command line as follows :

     spectre test.scs +escchars +log ./psf/spectre.out -format sst2 -raw ./psf

    and in simvision, I open the .trn file and I get the waveform at the bottom of the posting.  

    Printed below is the log file (sorry it's long.  I was hoping to attach it)

    ######

    START

    #####

     Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
    Version 10.1.1.128.isr9 32bit -- 30 May 2011
    Copyright (C) 1989-2010 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the p
    roperty of their respective holders.

    Protected by U.S. Patents:
            5,610,847; 5,790,436; 5,812,431; 5,859,785; 5,949,992; 5,987,238;
            6,088,523; 6,101,323; 6,151,698; 6,181,754; 6,260,176; 6,278,964;
            6,349,272; 6,374,390; 6,493,849; 6,504,885; 6,618,837; 6,636,839;
            6,778,025; 6,832,358; 6,851,097; 6,928,626; 7,024,652; 7,035,782;
            7,085,700; 7,143,021; 7,493,240; 7,571,401.

    Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

    User: Host: Memory  available: 13.1253 GB  physical: 135.2378 GB
    CPU Type: Intel(R) Xeon(R) CPU           X7560  @ 2.27GHz
              Processor PhysicalID CoreID Frequency
                  0         0        0     2261.1
                  1         1        0     2261.1
                  2         2        0     2261.1
                  3         3        0     2261.1
                  4         0        1     2261.1


    Simulating `test.scs' on  at 3:58:32 PM, Mon Jul 8, 2013 .
    Command line:
        /usr/cadence/MMSIM10_11_128/tools.lnx86/spectre/bin/32bit/spectre  \
            test.scs +escchars +log ./psf/spectre.out -format sst2 -raw  \
            ./psf

    Loading /usr/cadence/MMSIM10_11_128/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
    Loading /usr/cadence/MMSIM10_11_128/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
    Loading /usr/cadence/MMSIM10_11_128/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
    Loading /usr/cadence/MMSIM10_11_128/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...

    Time for NDB Parsing: CPU = 92.985 ms, elapsed = 439.466 ms.
    Time accumulated: CPU = 92.985 ms, elapsed = 439.466 ms.
    Peak resident memory used = 23.9 Mbytes.

    Existing shared object for module dynparam is up to date.
    Installed compiled interface for dynparam.

    Time for Elaboration: CPU = 26.996 ms, elapsed = 26.9861 ms.
    Time accumulated: CPU = 119.981 ms, elapsed = 466.696 ms.
    Peak resident memory used = 26.1 Mbytes.


    Time for EDB Visiting: CPU = 0 s, elapsed = 321.15 us.
    Time accumulated: CPU = 119.981 ms, elapsed = 467.215 ms.
    Peak resident memory used = 26.3 Mbytes.


    Notice from spectre during topology check.
        Only one connection to the following 2 nodes:
            0
            op


    Circuit inventory:
                  nodes 2
               dynparam 1
                vsource 1


    Time for parsing: CPU = 1.999 ms, elapsed = 4.54211 ms.
    Time accumulated: CPU = 122.98 ms, elapsed = 471.914 ms.
    Peak resident memory used = 26.9 Mbytes.


    ************************************************
    Transient Analysis `tran': time = (0 s -> 10 us)
    ************************************************

    Notice from spectre during transient analysis `tran'.
        The value of parameter 'period' is set to 1.000000e-07 at time 0.000000e+00.

    Important parameter values:
        start = 0 s
        outputstart = 0 s
        stop = 10 us
        step = 10 ns
        maxstep = 200 ns
        ic = all
        useprevic = no
        skipdc = no
        reltol = 1e-03
        abstol(V) = 1 uV
        abstol(I) = 1 pA
        temp = 27 C
        tnom = 27 C
        tempeffects = all
        errpreset = moderate
        method = traponly
        lteratio = 3.5
        relref = sigglobal
        cmin = 0 F
        gmin = 1 pS

    .......

    Notice from spectre at time = 350 ns during transient analysis `tran'.
        The value of parameter 'period' is set to 1.000000e-06 at time 3.500000e-07.

    ..................9..................8..................7..................6..................5..................4..................3..................2..................1..................0
    Number of accepted tran steps =             274
    Initial condition solution time: CPU = 0 s, elapsed = 430.107 us.

    Notice from spectre during transient analysis `tran'.
        The value of parameter 'period' is reset to the original value 1.000000e-07.

    Intrinsic tran analysis time:    CPU = 9.999 ms, elapsed = 10.1612 ms.
    Total time required for tran analysis `tran': CPU = 15.998 ms, elapsed = 15.4648 ms.
    Time accumulated: CPU = 147.976 ms, elapsed = 497.289 ms.
    Peak resident memory used = 31.3 Mbytes.


    Aggregate audit (3:58:33 PM, Mon Jul 8, 2013):
    Time used: CPU = 155 ms, elapsed = 505 ms, util. = 30.7%.
    Time spent in licensing: elapsed = 381 ms, percentage of total = 75.4%.
    Peak memory used = 31.3 Mbytes.
    Simulation started at: 3:58:32 PM, Mon Jul 8, 2013, ended at: 3:58:33 PM, Mon Jul 8, 2013, with elapsed time (wall clock): 505 ms.
    spectre completes with 0 errors, 0 warnings, and 4 notices.

    #######

    FINISH

    #######

    Don't understand the dotted lines.....but if you look at the plot below, you'll see there's no activity beyond 350ns

    Have I got a weird version of MMSIM/IUS?
    • Post Points: 5
  • Mon, Jul 8 2013 8:21 AM

    • KMan11
    • Not Ranked
    • Joined on Mon, Jun 10 2013
    • Bristol, Avon
    • Posts 8
    • Points 100
    Re: Dynamic parameter and verilogA code Reply
    Hi Andrew, 

     You'll see above, the image from my simvision of your code.  I run the following command from UNIX :

     spectre test.scs +escchars +log ./psf/spectre.out -format sst2 -raw ./psf

    test.scs contains the instantiations and analysis info

    Rest is as you have it

     I've attached a log of the run below (sorry its long).

    ////////

    START

    ///////

     Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
    Version 10.1.1.128.isr9 32bit -- 30 May 2011
    Copyright (C) 1989-2010 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the p
    roperty of their respective holders.

    Protected by U.S. Patents:
            5,610,847; 5,790,436; 5,812,431; 5,859,785; 5,949,992; 5,987,238;
            6,088,523; 6,101,323; 6,151,698; 6,181,754; 6,260,176; 6,278,964;
            6,349,272; 6,374,390; 6,493,849; 6,504,885; 6,618,837; 6,636,839;
            6,778,025; 6,832,358; 6,851,097; 6,928,626; 7,024,652; 7,035,782;
            7,085,700; 7,143,021; 7,493,240; 7,571,401.

    Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

    User: Host:    HostID: 220A0D01   PID: 22903
    Memory  available: 13.1253 GB  physical: 135.2378 GB
    CPU Type: Intel(R) Xeon(R) CPU           X7560  @ 2.27GHz
              Processor PhysicalID CoreID Frequency
                  0         0        0     2261.1
                  1         1        0     2261.1
                  2         2        0     2261.1
                  3         3        0     2261.1
                  4         0        1     2261.1
                  5         1        1     2261.1
                  6         2        1     2261.1
                  7         3        1     2261.1


    Simulating `test.scs' on at 3:58:32 PM, Mon Jul 8, 2013 (process id: 22903).
    Command line:
        /usr/cadence/MMSIM10_11_128/tools.lnx86/spectre/bin/32bit/spectre  \
            test.scs +escchars +log ./psf/spectre.out -format sst2 -raw  \
            ./psf

    Loading /usr/cadence/MMSIM10_11_128/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
    Loading /usr/cadence/MMSIM10_11_128/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
    Loading /usr/cadence/MMSIM10_11_128/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
    Loading /usr/cadence/MMSIM10_11_128/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...

    Time for NDB Parsing: CPU = 92.985 ms, elapsed = 439.466 ms.
    Time accumulated: CPU = 92.985 ms, elapsed = 439.466 ms.
    Peak resident memory used = 23.9 Mbytes.

    Existing shared object for module dynparam is up to date.
    Installed compiled interface for dynparam.

    Time for Elaboration: CPU = 26.996 ms, elapsed = 26.9861 ms.
    Time accumulated: CPU = 119.981 ms, elapsed = 466.696 ms.
    Peak resident memory used = 26.1 Mbytes.


    Time for EDB Visiting: CPU = 0 s, elapsed = 321.15 us.
    Time accumulated: CPU = 119.981 ms, elapsed = 467.215 ms.
    Peak resident memory used = 26.3 Mbytes.


    Notice from spectre during topology check.
        Only one connection to the following 2 nodes:
            0
            op


    Circuit inventory:
                  nodes 2
               dynparam 1
                vsource 1


    Time for parsing: CPU = 1.999 ms, elapsed = 4.54211 ms.
    Time accumulated: CPU = 122.98 ms, elapsed = 471.914 ms.
    Peak resident memory used = 26.9 Mbytes.


    ************************************************
    Transient Analysis `tran': time = (0 s -> 10 us)
    ************************************************

    Notice from spectre during transient analysis `tran'.
        The value of parameter 'period' is set to 1.000000e-07 at time 0.000000e+00.

    Important parameter values:
        start = 0 s
        outputstart = 0 s
        stop = 10 us
        step = 10 ns
        maxstep = 200 ns
        ic = all
        useprevic = no
        skipdc = no
        reltol = 1e-03
        abstol(V) = 1 uV
        abstol(I) = 1 pA
        temp = 27 C
        tnom = 27 C
        tempeffects = all
        errpreset = moderate
        method = traponly
        lteratio = 3.5
        relref = sigglobal
        cmin = 0 F
        gmin = 1 pS

    .......

    Notice from spectre at time = 350 ns during transient analysis `tran'.
        The value of parameter 'period' is set to 1.000000e-06 at time 3.500000e-07.

    ..................9..................8..................7..................6..................5..................4..................3..................2..................1..................0
    Number of accepted tran steps =             274
    Initial condition solution time: CPU = 0 s, elapsed = 430.107 us.

    Notice from spectre during transient analysis `tran'.
        The value of parameter 'period' is reset to the original value 1.000000e-07.

    Intrinsic tran analysis time:    CPU = 9.999 ms, elapsed = 10.1612 ms.
    Total time required for tran analysis `tran': CPU = 15.998 ms, elapsed = 15.4648 ms.
    Time accumulated: CPU = 147.976 ms, elapsed = 497.289 ms.
    Peak resident memory used = 31.3 Mbytes.


    Aggregate audit (3:58:33 PM, Mon Jul 8, 2013):
    Time used: CPU = 155 ms, elapsed = 505 ms, util. = 30.7%.
    Time spent in licensing: elapsed = 381 ms, percentage of total = 75.4%.
    Peak memory used = 31.3 Mbytes.
    Simulation started at: 3:58:32 PM, Mon Jul 8, 2013, ended at: 3:58:33 PM, Mon Jul 8, 2013, with elapsed time (wall clock): 505 ms.
    spectre completes with 0 errors, 0 warnings, and 4 notices.

     

    ///////

    FINISH

    ///////

    Do I have a bad version of IUS/MMSIM?

     

     

     

    • Post Points: 20
  • Mon, Jul 8 2013 12:52 PM

    Re: Dynamic parameter and verilogA code Reply

    I couldn't see your picture, but I tried in simvision and it worked fine for me (I was using MMSIM11.1 latest ISR). So I went back and used an old simvision (still OK). I then tried various MMSIM10.1 vintages (e.g. MMSIM10.1 ISR12) - and then I see the problem. I found that the problem was fixed in MMSIM10.1 ISR15:

    UNIX> spectre -V
    @(#)$CDS: spectre  version 10.1.1 32bit 09/21/2011 20:01 (usimamd64-13) $
    UNIX> spectre -W
    sub-version  10.1.1.235.isr15

    So the problem is that you have a version of MMSIM with a bug, now fixed.

    Regards,

    Andrew.

     

    • Post Points: 20
  • Tue, Jul 9 2013 1:46 AM

    • KMan11
    • Not Ranked
    • Joined on Mon, Jun 10 2013
    • Bristol, Avon
    • Posts 8
    • Points 100
    Re: Dynamic parameter and verilogA code Reply

     Hi Andrew,

    Thanks for going to the effort to itierate out the problem.  Can see the option to attach an image in the reply box, so I cut and pasted it...perhaps it was moderate.

    I'll ask if we can upgrade our MMSIM

     All the best

     

    KMan11

    • Post Points: 20
  • Tue, Jul 9 2013 1:51 AM

    Re: Dynamic parameter and verilogA code Reply

    Hi KMan11,

    Pasting images doesn't work (as far as I know), but you can upload images as attachments via the Options tab when replying to a post.

    Anyway, good luck with getting a newer version (there have been two major releases of MMSIM since the one you're using, by the way).

    Regards,

    Andrew.

    • Post Points: 20
  • Fri, Jul 12 2013 1:57 AM

    • KMan11
    • Not Ranked
    • Joined on Mon, Jun 10 2013
    • Bristol, Avon
    • Posts 8
    • Points 100
    Re: Dynamic parameter and verilogA code Reply

     Hi Andrew.

     

    Our Cad guy downloaded, built and installed Spectre 12.1.1 32 bit

    sub version : 12.1.1.059.isr10

     

    Attached is an image of shownig fast clocking and then slow clocking of the data from file

     

    Thanks for your help

     

     


    • Post Points: 5
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Started by KMan11 at 04 Jul 2013 10:57 AM. Topic has 7 replies.