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 what do you mean by assertion block 

Last post Wed, Jul 3 2013 11:28 PM by maheshs. 1 replies.
Started by BharathECE 03 Jul 2013 11:19 PM. Topic has 1 replies and 421 views
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  • Wed, Jul 3 2013 11:19 PM

    • BharathECE
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    • Joined on Fri, Mar 22 2013
    • Hyderabad, Andhra Pradesh
    • Posts 12
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    what do you mean by assertion block Reply

    Hi

    Iam having some of the assertions result as block.What do you mean by block and how to make those assertions passing or failing. 

     

    Thanks

    Bharath 

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    • Post Points: 20
  • Wed, Jul 3 2013 11:28 PM

    • maheshs
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    • Joined on Fri, Aug 7 2009
    • Posts 3
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    Re: what do you mean by assertion block Reply

    IFV can display the status of an assertion as ‘blocked’ if it detects any combinational loop in the signals involved in the assertion's cone-of-influence. The status ‘blocked’ indicates that the assertion could not be verified, because combinational loops exist in the design. Please follow below steps to identify and resolve the combinational loops.

    Step - 1:

    If you get a blocked status, first of all, please run the following command for the blocked assertion. It will let you know if indeed the assertion was blocked because of combinational loops.

    formalVerifier> assertion –show <blocked_assertion_name > -verbose

    For example

    formalVerifier> assertion –show my_assertion –verbose
    my_assertion: Block (0)
    Combinational loop(s) found in the design. Use the debug command to view the nets involved in the combinational loop(s).


    Step 2:

    Now you would be interested in knowing which module has combinational loops and what signals are involved? In order to get this information, please run the "debug" command as suggested below.

    formalverifier> debug my_assertion

    Counter-example launched.
    Number of combinational loop : 1
    1) Net(s) in combinational loop : 2
    combinational_loop.Y (File: ./test.sv)
    combinational_loop.W (File: ./test.sv)

    So now we know that Y, W are the signals involved. It also points out the file name where those signals are declared. We can now easily check the indicated code and remodel the HDL to remove the combinational loop.

    Thanks

    -Mahesh Soni

     

    • Post Points: 5
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Started by BharathECE at 03 Jul 2013 11:19 PM. Topic has 1 replies.