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 SystemVerilog Assertions: Property Library 

Last post Wed, Jul 3 2013 1:13 PM by Paulo Pinzani. 0 replies.
Started by Paulo Pinzani 03 Jul 2013 01:13 PM. Topic has 0 replies and 493 views
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  • Wed, Jul 3 2013 1:13 PM

    SystemVerilog Assertions: Property Library Reply

     Hi Everyone!

    Im new in this whole SV Assertions world, and Im having some troubles trying to define a "property library". Basically, what I want to do, is to have all my properties definitions in a separate file, and to have the assert property ... setences in a separate file, in order to use the one property in more than one assertion file.The problem is thatI cant find a way to acces to the property definition from the assertion file.

    Is there any way to achieve this? Because all the documentation I have seen, have the property declaration and the assert directive in the same file.

    Thank You,

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Started by Paulo Pinzani at 03 Jul 2013 01:13 PM. Topic has 0 replies.