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 How to import large verilog netlist into cadence schematic? 

Last post Mon, Jun 24 2013 1:52 PM by mliang. 2 replies.
Started by mliang 15 Jun 2013 08:32 AM. Topic has 2 replies and 659 views
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  • Sat, Jun 15 2013 8:32 AM

    • mliang
    • Not Ranked
    • Joined on Tue, May 21 2013
    • Posts 2
    • Points 25
    How to import large verilog netlist into cadence schematic? Reply

    The verilog netlist contains more than 40 thousands component. When I import the netlist into cadence, it gives me an error of "Illegal bus reference - Can't tap "Neta" from "Netb".". I looked through the generated schematic, it messed up Neta and Netb.  I cheked the Schematic Generation Options befoe importing the netlist again. The Maximum number of Rows/columns are limited to 1024. Is it possible to increase the Maximum Number of Rows/Columns of the schmatic before importing the large netlist?

     

    Thanks,

    • Post Points: 20
  • Mon, Jun 24 2013 1:42 PM

    Re: How to import large verilog netlist into cadence schematic? Reply

    I suggest you contact customer support. You didn't say which version you're using - which is quite important as there have been a number of fixes related to Verilogin.

    You could always turn off the Full Place & Route option, so that it doesn't attempt to fully route the schematic. You could also decrease the density - it's a slider on the form. But without knowing what the real issue, it's hard to be sure. 1024x1024 should be OK for 40k components.

    Andrew.

     

    • Post Points: 20
  • Mon, Jun 24 2013 1:52 PM

    • mliang
    • Not Ranked
    • Joined on Tue, May 21 2013
    • Posts 2
    • Points 25
    Re: How to import large verilog netlist into cadence schematic? Reply
    Thanks very much. It is helpful. I will try it and to see what happens.
    • Post Points: 5
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Started by mliang at 15 Jun 2013 08:32 AM. Topic has 2 replies.