My guess is that you're simulating using AMS? Or are you using spectreVerilog or ultrasimVerilog? Maybe you have one of these variables in a .simrc file or .cdsinit somewhere:
In Tools->NC Verilog, this corresponds to the "Generate Verilog Test Fixture Template" option on Setup->Netlist. In UltraSimVerilog (and spectreVerilog, I think - I only checked one of them), this is on Setup->Environment and then the "Verilog Netlist Option" button.
I don't know whether this impacts AMS simulation or not.
And it's only a warning...