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 verilog simulation 

Last post Mon, May 13 2013 9:09 AM by Andrew Beckett. 5 replies.
Started by apple419 12 May 2013 06:34 PM. Topic has 5 replies and 1027 views
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  • Sun, May 12 2013 6:34 PM

    • apple419
    • Top 500 Contributor
    • Joined on Fri, Apr 19 2013
    • Norristown, PA
    • Posts 35
    • Points 550
    verilog simulation Reply

    Hi, Cadence users,

        In the process of learning Cadence...

        I created a new cell adder8 with Verilog functional view. Its symbol is also created. Now there are two views for adder8. One is functional view, and the other is symbol view.

        My question now is how do I simulate it (digitally)?

        Should I use NC-verilog? In CIW I chose tools ->  NC-verilog. The verilog environment for NC-verilog integration form appears.

        Then I filled in the Run directory, Top level design (library, cell, view), and the simulation mode (interactive), selected all three options (compile, elaborate, simulate.) 

         What is next? initialize design? generate netlist?...

        I am a beginner Cadence user. So could anyone describe the detail step by step direction? Or is there such tutorial available in this forum?

        I am using Cadence IC615. 

    Thank you!

    Best regards

      

    • Post Points: 20
  • Mon, May 13 2013 1:51 AM

    Re: verilog simulation Reply

    Might be worth looking in the banner of the window...


    • Post Points: 20
  • Mon, May 13 2013 8:16 AM

    • apple419
    • Top 500 Contributor
    • Joined on Fri, Apr 19 2013
    • Norristown, PA
    • Posts 35
    • Points 550
    Re: verilog simulation Reply

    Hi Andrew,

       Thanks for your help. Actually I already read the help document (Virtuoso NC Verilog Environment User Guide) but I still can not get it right.

        Based on the simulation process flowchart on page 66, at the second step " Set up NC Verilog Integration for simulation", when I clicked the "initialize design" button on the left side of the window, an error pops up and says:

        ERROR (VLOGUI-18): failed to start simulation. The NC-verilog Executable field on the Simulation Setup form should not be left blank. Specify the NC-Verilog executable nama and try again.

        Then I selected setup -> simulation and opened the simulation setup form. There almost at the bottom I saw:

         NC-Verilog Executable: ncxlmode

        I did not fill the form. The content is already there when the form is opened. I guess it is the default setting?

        So the NC-Verilog executable field is not blank.

        But, is "ncxlmode" probematic?

    Best regards

    apple419 

     

     

    • Post Points: 20
  • Mon, May 13 2013 8:28 AM

    Re: verilog simulation Reply

    Apologies - you didn't mention that you'd read the documentation (and I couldn't guess that from your reply).

    Most likely you don't have the INCISIVE software in your UNIX path. You need to ensure that you have a release (e.g. INCISIV121 or INCISIV122) installed, and then <INCISIVinstDir>/tools/bin in your UNIX path. In the UNIX shell you should be able to type "which ncxlmode" and see that it finds it.

    Regards,

    Andrew.

     

    • Post Points: 20
  • Mon, May 13 2013 8:55 AM

    • apple419
    • Top 500 Contributor
    • Joined on Fri, Apr 19 2013
    • Norristown, PA
    • Posts 35
    • Points 550
    Re: verilog simulation Reply

    Andrew,

       Thanks for your reply. No, it is my fault. I did not mention it. Sorry about that.

       I typed "which ncxlmode" and it returned: ncxlmode: command not found. 

       When I typed "which ncverilog", it returned /home/users/cad/bin/ncverilog. So I assume "ncverilog" would be the executable. But when I changed ncxlmode to ncverilog and ok, it still gave me the same error.

       How do I know if INCISIV is installed, or if my environment setup is right?  

       I checked /home/users/cad/bin directory, and I saw: 

        ncelab -> incisive*

        ncshell -> incisive*

    ncsim -> incisive*

    ncverilog -> incisive*

    ncvlog -> incisive*

    ncvhdl -> incisive*

     

    Best Regards 

    Apple419 

    • Post Points: 20
  • Mon, May 13 2013 9:09 AM

    Re: verilog simulation Reply

    It appears you have some wrappers installed in your environment which are taking care of running the real tools underneath. I suggest that you speak to whoever is responsible for those at your site. I've no idea what they do or how they are set up (maybe you can do "cat /home/users/can/bin/ncvlog" to see the contents of the wrapper script to see if that offers any clues.

    It seems that there's no wrapper been created for ncxlmode.

    Regards,

    Andrew.

     

    • Post Points: 5
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Started by apple419 at 12 May 2013 06:34 PM. Topic has 5 replies.