There are two kind of warnings always happened during synthesis. I checked them in the user manual but I do not know how to solve them.
1. The following primary outputs have no clocked external delays. As a result the timing paths leading to the ports have no timing constraints derived from clock aveforms. The'external_delay' command is used to create new external delays.
2.There is 1 CSA group in module 'FIFO_csa_cluster_33'... Rejected. Somtimes it is accepted. sometimes it is rejectd. What is CSA group?
Could you please give me some advieces to fix these problems?
Thank you very much.