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 Transmission_Gate(TGX1) LIB Generation using Encounter Library Characterizer ELC Problem  

Last post Sun, May 5 2013 9:18 AM by Hatkar. 0 replies.
Started by Hatkar 05 May 2013 09:18 AM. Topic has 0 replies and 563 views
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  • Sun, May 5 2013 9:18 AM

    • Hatkar
    • Not Ranked
    • Joined on Thu, Feb 21 2013
    • Posts 3
    • Points 30
    Transmission_Gate(TGX1) LIB Generation using Encounter Library Characterizer ELC Problem Reply

    My TGX1 is Tristate Gate and Not Bidirectional Tristate Gate, Gate file Generated is as follows

    DESIGN ( TGX1 );
        //    =================
        //     PORT DEFINITION
        //    =================
            INPUT NG ( NG );
            INPUT PG ( PG );
            INOUT D ( D );
            INOUT S ( S );
            SUPPLY0 GND ( GND );
            SUPPLY1 VDD ( VDD );
            -COMPLEMENTARY ( NG, PG );
        //    ===========
        //     INSTANCES
        //    ===========
            CMOSX ( S, D, NG, PG );
        END_OF_DESIGN;

    CMOS is a Tristate Gate and CMOSX is Bidirectional Tristate Gate.
    CMOSX has to be replaced with Primitive or Tirstate Gates according to ECL User Guide  

    After Replacing  CMOSX, Gate File is as follows

    DESIGN ( TGX1 );
        //    =================
        //     PORT DEFINITION
        //    =================
            INPUT NG ( NG );
            INPUT PG ( PG );
            INPUT D ( D );
            OUTPUT S ( S, NG, PG );
            SUPPLY0 GND ( GND );
            SUPPLY1 VDD ( VDD );
            -COMPLEMENTARY ( NG, PG );
        //    ===========
        //     INSTANCES
        //    ===========
            CMOS ( S, D, NG, PG );   
        END_OF_DESIGN;

    Generated 8 vectors, Total Simulation Passed 8 (100.00%), generated *.alf, *.lib and *.v file successfully.

    *.v verilog file generated is as follows
         module TGX1 (D, NG, PG, S);
                input    D, NG, PG;
                output    S;
                bufif1 (S, D, NG);
         endmodule

    I think instead of BUFIF1 (S, D, NG) it should infer CMOS ( S, D, NG, PG).

    Please let me know whether whether my above verilog file is correct for TGX1,

    if not suggest me any alternative to replace the Bidirectional Switch CMOSX in Gate File, so that generated verilog code will have CMOS Tristate Gate and the code will be as follows

    module TGX1 (D, NG, PG, S);
                input    D, NG, PG;
                output    S;
               
    cmos ( S, D, NG, PG);
         endmodule
       

    Thanks

    • Post Points: 5
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Started by Hatkar at 05 May 2013 09:18 AM. Topic has 0 replies.