I have some doubts regarding clock tree generation and routing. I am just a beginner in this field, so certain question might seem trivial:
1. Is the CTS done before the routing process or after the routing process.
2. I was trying the optimisation option in SOC encounter before routing and it inserts buffers for the two clocks which I have in the design. Can i do the optimisation after the CTS as I donot want these buffers to be added before CTS as it doesnot detect the entire path when I do the CTS. Only till the first buffer.
3. I have a pad
BD3CRUDQP_1V2_SF_LIN PAD_N_Clk ( .A(1'b0), .TA(1'b0), .TM(1'b0), .EN(1'b1),
.TEN(1'b0), .IO(Clk_PAD), .PDN(1'b1), .PUN(1'b0), .ZI(Clk) );
While doing the CTS, in the .ctstch file should i mention PAD_N_CLK/ZI in the AutoCTSRootPin option or is there any other command for IO pads?
4. I tried doing CTS after the rooting and found a lot of DRC errors when I did the verify geometry. What may be the problem? Should I now run the optimisation of the design command?