Here's what I've done:
I created a counter in schematic virtuoso, after that I created its symbol.
Whith ENCOUNTER i generated its layout, I routed it but I clould not do Timing delay I don't know why?
After I saved in gds file: Map File=> streamOut.map; Library Name=> DesigneLib; I checked "Uniquify Cell Names" and "White abstract information for LEF Macros"
To import it: file- import- stream then I just checked "Generate Technology Information From Stream File" then apply
Then here I have not any error or warning !
The problem then, is the fact that the layout isn't imported correctly since the metal1 and all the connections made of metal1 aren't displayed (or not imported).
In addition to that, while running the lvs, I obtain a lot of warnings informing me that all my transistors aren't recognized.
I don't know if I need to detail more ? that's exactly all what I did ! Can you please have any explanation.
Thanks for your patience!