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 Problem in Cadence Virtuoso AC analysis 

Last post Tue, Apr 2 2013 2:01 PM by OneNewBoy. 7 replies.
Started by OneNewBoy 21 Mar 2013 08:08 PM. Topic has 7 replies and 2825 views
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  • Thu, Mar 21 2013 8:08 PM

    • OneNewBoy
    • Not Ranked
    • Joined on Thu, Feb 14 2013
    • Posts 13
    • Points 200
    Problem in Cadence Virtuoso AC analysis Reply

    Hi all,

    I am facing an often discussed problem  while simulating a differential pair in cadence virtuoso.

    Though I have biased the transistors through DC  (though they are in subthreshold mode), yet when I try do do ac analysis (I follow all regular steps) I get a zero magnitude at output. Ths schematic is attached.

    Can someone help me in debugging this ?

     

     

    • Post Points: 20
  • Thu, Mar 21 2013 11:58 PM

    Re: Problem in Cadence Virtuoso AC analysis Reply

    You probably didn't set the AC magnitude on your input source. I see you have a sine source there, but that won't help in an AC simulation. There is a separate parameter to set the magnitude of the input signal. It's a bit hard to see in your picture - you might have set it in which case your Vac variable needs to be non-zero.

    Other than that, your circuit is probably connected up incorrectly.

    Maybe you can post the input.scs from your simulation (the netlist) and then it's easier to take a look?

    Regards,

    Andrew.

    • Post Points: 20
  • Fri, Mar 22 2013 11:51 AM

    • OneNewBoy
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    • Joined on Thu, Feb 14 2013
    • Posts 13
    • Points 200
    Re: Problem in Cadence Virtuoso AC analysis Reply

    Hi Andrew, Thanks a lot for help. Please find below the contents of the netlist:  

    // Generated for: spectre

    // Generated on: Mar 22 14:37:53 2013

    // Design library name: Basic_Blocks

    // Design cell name: DiffAmp_MOS

    // Design view name: schematic

    simulator lang=spectre

    global 0 vdd!

    parameters C=2p Ibias=1u Vac=0.1 VDD=0.4 VinNDC=0.2 VinPDC=0.2 Wnl=7 Wpl=7

     

    // Library name: Basic_Blocks

    // Cell name: DiffAmp_MOS

    // View name: schematic

    I2 (net2 0) isource dc=Ibias type=dc

    V2 (VinN 0) vsource dc=VinNDC type=dc

    V3 (net012 0) vsource dc=VinPDC type=dc

    V0 (vdd! 0) vsource dc=VDD type=dc

    C0 (Vout 0) capacitor c=C

    Vac (VinP net012) vsource dc=0 mag=Vac phase=0 type=sine sinedc=0 ampl=Vac \

            sinephase=0 freq=1K

    I21 (net3 net3 vdd!) SubPMOS_noisy W=Wpl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \

            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=1.25e+10

    I20 (Vout net3 vdd!) SubPMOS_noisy W=Wpl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \

            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=1.25e+10

    I23 (Vout VinN net2) SubNMOS_noisy W=Wnl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \

            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=5e+09

    I22 (net3 VinP net2) SubNMOS_noisy W=Wnl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \

            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=5e+09

    simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \

        tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \

        digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \

        checklimitdest=psf

    ac ac start=1 stop=1G dec=20 save=all annotate=status

    modelParameter info what=models where=rawfile

    element info what=inst where=rawfile

    outputParameter info what=output where=rawfile

    designParamVals info what=parameters where=rawfile

    primitives info what=primitives where=rawfile

    subckts info what=subckts  where=rawfile

    saveOptions options save=allpub currents=all

    ahdl_include "~/Library_userDefined/Basic_Blocks/SubPMOS_noisy/veriloga/veriloga.va"

    ahdl_include "~/Library_userDefined/Basic_Blocks/SubNMOS_noisy/veriloga/veriloga.va" 

    • Post Points: 20
  • Sat, Mar 23 2013 3:50 AM

    Re: Problem in Cadence Virtuoso AC analysis Reply

    My guess is that there's either something wrong with your models, or that the dimensions passed in are wrong. For example, your L is 20nm, but the W is 7 metres!

    I did some adjustment (I don't have your models, so I made some up), and it's simulating OK for me:

     // Generated for: spectre
    // Generated on: Mar 22 14:37:53 2013
    // Design library name: Basic_Blocks
    // Design cell name: DiffAmp_MOS
    // Design view name: schematic
    simulator lang=spectre
    global 0 vdd!
    parameters C=2p Ibias=1u Vac=0.1 VDD=0.4 VinNDC=0.2 VinPDC=0.2 Wnl=7 Wpl=7
     
    // very simple models because I don't have your models...
    inline subckt SubNMOS_noisy (d g s)
     parameters W=1 L=1
     SubNMOS_noisy (d g s 0) nch w=W*1u l=L*10
     model nch bsim4 type=n
    ends SubNMOS_noisy

    inline subckt SubPMOS_noisy (d g s)
     parameters W=1 L=1
     SubPMOS_noisy (d g s s) pch w=W*1u l=L*10
     model pch bsim4 type=p
    ends SubPMOS_noisy

    // Library name: Basic_Blocks
    // Cell name: DiffAmp_MOS
    // View name: schematic
    I2 (net2 0) isource dc=Ibias type=dc
    V2 (VinN 0) vsource dc=VinNDC type=dc
    V3 (net012 0) vsource dc=VinPDC type=dc
    V0 (vdd! 0) vsource dc=VDD type=dc
    C0 (Vout 0) capacitor c=C
    Vac (VinP net012) vsource dc=0 mag=Vac phase=0 type=sine sinedc=0 ampl=Vac \
            sinephase=0 freq=1K
    I21 (net3 net3 vdd!) SubPMOS_noisy W=Wpl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \
            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=1.25e+10
    I20 (Vout net3 vdd!) SubPMOS_noisy W=Wpl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \
            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=1.25e+10
    I23 (Vout VinN net2) SubNMOS_noisy W=Wnl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \
            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=5e+09
    I22 (net3 VinP net2) SubNMOS_noisy W=Wnl Temp=300 Gamma=1.2 Kox=12 L=2e-08 \
            Nit=1e+16 Tox_P=2.5e-09 Trap_depth=2e-09 attn=5e+09
    simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
        tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
        digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
        checklimitdest=psf
    ac ac start=1 stop=1G dec=20 save=all annotate=status
    modelParameter info what=models where=rawfile
    element info what=inst where=rawfile
    outputParameter info what=output where=rawfile
    designParamVals info what=parameters where=rawfile
    primitives info what=primitives where=rawfile
    subckts info what=subckts  where=rawfile
    saveOptions options save=allpub currents=all
    //ahdl_include "~/Library_userDefined/Basic_Blocks/SubPMOS_noisy/veriloga/veriloga.va"
    //ahdl_include "~/Library_userDefined/Basic_Blocks/SubNMOS_noisy/veriloga/veriloga.va"

    (I fiddled with the lengths, because  I got very little gain with the values you'd entered, but my models are completely artificial).

    Regards,

    Andrew.

    • Post Points: 20
  • Sat, Mar 23 2013 9:14 AM

    • OneNewBoy
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    • Joined on Thu, Feb 14 2013
    • Posts 13
    • Points 200
    Re: Problem in Cadence Virtuoso AC analysis Reply
    Thanks a lot Andrew for reply. Actually W=7 implies 7um as my current values are taken from a look-up table called by the verilog-A model, which has current values normalized in um. Anyways I will experiment and try again.
    • Post Points: 5
  • Mon, Mar 25 2013 9:01 AM

    • OneNewBoy
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    • Joined on Thu, Feb 14 2013
    • Posts 13
    • Points 200
    Re: Problem in Cadence Virtuoso AC analysis Reply

    Hi Andrew,

    I had a little doubt on what parameters are explicitly needed for ac analysis. This is because I am using verilog -A based models and hence want to be sure if I am doing the right thing.

    As far as I know, AC analysis first computes the DC operating point: so I must define current at each operating/gate voltage.

    Now at that particular operating point, I expect that spectre automatically computes all variables like transconductance/output resistance etc., which it will use in the linearized model representation of the circuit.

    So I wish to know if I need to provide these variables explicitly at each operating point and somehow include them in building a small signal model, to get MOSFET drain current as function of small signal inputs ?

    Thanks a lot ! 

    • Post Points: 20
  • Mon, Apr 1 2013 10:46 AM

    Re: Problem in Cadence Virtuoso AC analysis Reply

    Actually, spectre will linearize your VerilogA model and simulate that in the AC analysis. You should not have to write an explicit AC model (and in fact you can't really). Not sure what your model looks like, but maybe you've written it in a way that can't be transformed into a small signal model?

    Regards,

    Andrew.

    • Post Points: 20
  • Tue, Apr 2 2013 2:01 PM

    • OneNewBoy
    • Not Ranked
    • Joined on Thu, Feb 14 2013
    • Posts 13
    • Points 200
    Re: Problem in Cadence Virtuoso AC analysis Reply
    Ohh thanks ! that cleared my doubt ! My Verilog A model is pretty simple :) Spectre should be doing the right thing.
    • Post Points: 5
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Started by OneNewBoy at 21 Mar 2013 08:08 PM. Topic has 7 replies.