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 CMOS analog delay circuit help 

Last post Thu, Mar 28 2013 11:54 AM by Andrew Beckett. 18 replies.
Started by Donatello 13 Mar 2013 02:38 PM. Topic has 18 replies and 3280 views
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  • Sat, Mar 16 2013 4:04 PM

    • Donatello
    • Not Ranked
    • Joined on Thu, Dec 6 2012
    • Posts 14
    • Points 175
    Re: CMOS analog delay circuit help Reply
    Hi Andrew, You said something about your first stage of BBD working? Anyone else want to help? Thanks.
    • Post Points: 20
  • Sat, Mar 23 2013 5:31 AM

    Re: CMOS analog delay circuit help Reply

    I disconnected to the right of the first capacitor so that it wasn't connected to the next stage. Then it was sampling the input onto the first capacitor (not surprising, really).

    Good luck with your circuit!

    Andrew

    • Post Points: 20
  • Tue, Mar 26 2013 2:50 PM

    • Donatello
    • Not Ranked
    • Joined on Thu, Dec 6 2012
    • Posts 14
    • Points 175
    Re: CMOS analog delay circuit help Reply
    Hey Andrew, The first capacitor is grounded and the rest are all between the gate and the drain. So were you able to see any delay at all? All i get is clocking glitches
    • Post Points: 20
  • Thu, Mar 28 2013 11:54 AM

    Re: CMOS analog delay circuit help Reply

    Can't remember - I only looked at it briefly. I suggest a more design-centric focused forum may be a better choice (such as http://www.designers-guide.org  - as I mentioned before).

    Regards,

    Andrew.

    • Post Points: 5
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Started by Donatello at 13 Mar 2013 02:38 PM. Topic has 18 replies.