Home > Community > Forums > Feedback, Suggestions, and Questions > Mixed language simulation

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Mixed language simulation 

Last post Fri, Feb 15 2013 5:49 AM by Jayakirthi. 0 replies.
Started by Jayakirthi 15 Feb 2013 05:49 AM. Topic has 0 replies and 307 views
Page 1 of 1 (1 items)
Sort Posts:
  • Fri, Feb 15 2013 5:49 AM

    • Jayakirthi
    • Not Ranked
    • Joined on Thu, Feb 14 2013
    • Bangalore, Karnataka
    • Posts 1
    • Points 5
    Mixed language simulation Reply
    Hi, Can anyone help me how to simulate UVM testbench with SystemC design at pin level in cadence tool.. How to set UVM lib path and Systemc path and compile it.... please suggest what to refer or give an example
    I am new to cadence tools, your information will be very helpfull.
    Thank you vry much in advance
    • Post Points: 5
Page 1 of 1 (1 items)
Sort Posts:
Started by Jayakirthi at 15 Feb 2013 05:49 AM. Topic has 0 replies.