Home > Community > Forums > Logic Design > How to handle pre defined generated clocks in .libs.

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 How to handle pre defined generated clocks in .libs. 

Last post Fri, Jan 4 2013 8:28 AM by sureshm. 0 replies.
Started by sureshm 04 Jan 2013 08:28 AM. Topic has 0 replies and 764 views
Page 1 of 1 (1 items)
Sort Posts:
  • Fri, Jan 4 2013 8:28 AM

    • sureshm
    • Top 500 Contributor
    • Joined on Tue, Feb 1 2011
    • Posts 21
    • Points 345
    How to handle pre defined generated clocks in .libs. Reply

    Hi, 

     In the .libs, generated clock statements help defining the internal clocks being used in the entire design. When the .lib is design, internal clocks are reported or defined with the hierarchy of its instance, with a lot of complex naming conventions.

    Is there a way to control the naming conventions..

     For example

        a generated clock g1, is internal clock of IP lib ( IP_A).  IP_A is for example is instanced under  U_A_m/U_B_sm/U_C_sm

       g1 clock definition in the design is reported as  U_A_m\/U_B_sm\/U_C_sm\/U_IP_A\/g1

       The above definition makes the further constraints defining very difficult in the flow on these clocks.

      Is there a way to instruct the RC tool to honor then naming of the clock defined by the user as oppose the tool giving its own names .

      Thanks for the help!! 

     

    Suresh  

    • Post Points: 5
Page 1 of 1 (1 items)
Sort Posts:
Started by sureshm at 04 Jan 2013 08:28 AM. Topic has 0 replies.