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 Is it possible for VHDL to use a verilog/systemverilog package ? 

Last post Tue, Jan 8 2013 5:25 AM by Xinwei. 3 replies.
Started by Xinwei 10 Dec 2012 01:26 PM. Topic has 3 replies and 1440 views
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  • Mon, Dec 10 2012 1:26 PM

    • Xinwei
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    • Joined on Wed, Jan 4 2012
    • Posts 7
    • Points 80
    Is it possible for VHDL to use a verilog/systemverilog package ? Reply

     Hi all,

     I want to know if I compile one systemverilog package in a library, then in vhdl side, can it access the element in this package ? 

    For example .

    //file pkg.sv

    package pkg;

    const int a =10;

    endpackage

     

    // //file  tb.vhd

    library pkg_lib;

    use pkg_lib.pkg.all;

    ......

     

    I compile it by

    'irun -makelib pkg_lib pkg.sv -endlib'  

    'irun -reflib INCA_libs/pkg_lib tb.vhd '

     

    I got the error complaining the package pkg cannot be found in the library.  I want to know whether it is impossible to access a systemverilog package from the VHDL code , or I missed something ?  Thanks a lot !

    Best regards, 

    Xinwei 

    • Post Points: 20
  • Tue, Jan 8 2013 2:51 AM

    Re: Is it possible for VHDL to use a verilog/systemverilog package ? Reply
    I'm using Incisive 12.10.006 and to date I haven't found any way to make this possible. I've just had to rewrite the packages in VHDL for the moment! Regards, Jason
    • Post Points: 20
  • Tue, Jan 8 2013 5:14 AM

    • StephenH
    • Top 25 Contributor
    • Joined on Tue, Sep 2 2008
    • Bristol, Avon
    • Posts 258
    • Points 4,100
    Re: Is it possible for VHDL to use a verilog/systemverilog package ? Reply

    Hi Jason.

    This isn't currently possible, but I'm collecting requirements from users and am working on a solution. Please can you let me know the details of what you need to access from the VHDL package? Feel free to PM me or email to stephenh@cadence.com if you'd prefer not to discuss the details in public. 

    Thanks! 

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
    • Post Points: 5
  • Tue, Jan 8 2013 5:25 AM

    • Xinwei
    • Not Ranked
    • Joined on Wed, Jan 4 2012
    • Posts 7
    • Points 80
    RE: Is it possible for VHDL to use a verilog/systemverilog package ? Reply
    Hi Stephen and Jason´╝î
     
    Thanks for your reply.
     
    By the way, I have another question related to the package access (Or It is not only for pkg, but for the common access).
     
    For example,
     
    I have a source file src.sv that has a line "import pkg1::*;".   The pkg1 is defined in the file pkg1.sv.  Then I compile it by the following way:
     
    irun -c pkg1.sv -makelib lib1 src.sv -endlib
     
    In this situation, pkg1 is invisible for src.sv that compiled into lib1.  I know how to workaround this problem. But I still want to ask do you do this on purpose or maybe you can improve this to make pkg1.sv visible to src.sv even if it is compiled into a library.
     
    Please correct me if I misunderstand anything.
     
    Thanks and best regards,
    Xinwei
    • Post Points: 5
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Started by Xinwei at 10 Dec 2012 01:26 PM. Topic has 3 replies.