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 Problem with auto via  

Last post Sat, Nov 17 2012 10:42 AM by Andrew Beckett. 1 replies.
Started by 2221 05 Nov 2012 10:08 PM. Topic has 1 replies and 627 views
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  • Mon, Nov 5 2012 10:08 PM

    • 2221
    • Not Ranked
    • Joined on Mon, Jun 11 2012
    • Posts 4
    • Points 80
    Problem with auto via Reply

    Hi Everyone,

                I usually insert vias using  "create via " with "auto vias" enabled, on M2 and M1 overlap it will insert "M2_M1" via.  But, I want "M2_M1c" via.  Can anyone tell me how to do it . I mean the tool has to insert "M2_M1c" automatically instead of "M2_M1" via.

    Thanks,

    Srinivas.

    • Post Points: 20
  • Sat, Nov 17 2012 10:42 AM

    Re: Problem with auto via Reply

    Srinivas,

    Assuming you're using IC61X, I'd suggest that you create a constraint group with a validVias constraint which only contains the vias you wish to use. This can be done either by writing one in your technology database (from an ASCII tech file) - it could be added into an incremental technology database or even your design library if you "reference" rather than "attach" the technology lib. Or you could use the Process Rule Editor in the Constraint Manager (VLS XL or GXL) to add the new constraint group to the library or design, and define the validVias constraint within that group through the Process Rule Editor.

    Having done this, you can use Options->Editor to pick the constraint group you want to use for Vias (you can always switch it back if you want other vias used for other things).

    Regards,

    Andrew.

    • Post Points: 5
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Started by 2221 at 05 Nov 2012 10:08 PM. Topic has 1 replies.