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 RTL Compiler synthesis commands for TDC design 

Last post Thu, Nov 1 2012 9:06 AM by Maheshnb. 0 replies.
Started by Maheshnb 01 Nov 2012 09:06 AM. Topic has 0 replies and 914 views
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  • Thu, Nov 1 2012 9:06 AM

    • Maheshnb
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    • Joined on Thu, Nov 1 2012
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    RTL Compiler synthesis commands for TDC design Reply

    Greeting to all,

            I have written code for inverter chain which uses LVT and HVT cell to have slow and fast path for my vernier Time to digital converter......

    my  first quesrtion is

    is it possible to synthesize this from gpdk library from cadence??????

    if so please provide me the RTL compiler command list

     

    mahesh

    • Post Points: 5
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Started by Maheshnb at 01 Nov 2012 09:06 AM. Topic has 0 replies.