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 How to generate ports in cellview for global pins? 

Last post Tue, Oct 23 2012 3:21 PM by bjbit. 0 replies.
Started by bjbit 23 Oct 2012 03:21 PM. Topic has 0 replies and 537 views
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  • Tue, Oct 23 2012 3:21 PM

    • bjbit
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    • Joined on Tue, Mar 6 2012
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    How to generate ports in cellview for global pins? Reply

    Hi,

    I am using IC614 with technology of IBM7RF. I got comfused with the usage of global pins while working on the design flow of P&R and LVS. I have tried to name power and ground pins as normal I/O pins "vdd" "vss" in my standard cells. This way works fine in P&R to get design layout. But it causes "unbound pins" errors in LVS (no other errors). I am not sure if I can ignore these errors and trust that the P&R layout actually matches with the schematic. 

    Now I name power and ground as global jumper pins "vdd!" and "vss!". However, the generated standard cellview doesn't have ports for them, as the picture shown. In this case, there is not global pins' definitions from generated verilog netlist. And P&R encounter cannot specify power nets. Anything I am missing? Or is there better way to solve this issue? Thanks in advance.

    Best regards, 


    • Post Points: 5
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Started by bjbit at 23 Oct 2012 03:21 PM. Topic has 0 replies.