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 Outputting a synthesized file in reverse order 

Last post Sat, Oct 13 2012 12:44 PM by Ankur S. 0 replies.
Started by Ankur S 13 Oct 2012 12:44 PM. Topic has 0 replies and 702 views
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  • Sat, Oct 13 2012 12:44 PM

    • Ankur S
    • Not Ranked
    • Joined on Sat, Oct 13 2012
    • Posts 2
    • Points 10
    Outputting a synthesized file in reverse order Reply

     Hi,

     I wanted to write the output of a synthesized verilog file in reverse order. Here is an example. If rtl compiler (RC) generates the following:

    module .. (..) ;

    // list of wires

    ...

    // gate-level netlist (let's say there are only three gates)

     AND2_X1 (...);

    OR2_X1 (...) ;

    INV_X1 (...);

    endmodule

     

    What I would like to see is as follows:

     

    module .. (..) ;

    // list of wires

    ...

    // gate-level netlist (netlist is reversed)

    INV_X1 (...); 

    OR2_X1 (...) ;

     AND2_X1 (...);

     endmodule

    Is there a command in RC that reverses the order in which netlist is written. I want to do this because it was observed that inputs of upper gates are outputs of lower gates. I need to use this netlist in C++ code and there, with the orginial ordering, I would get incorrect output. I can ofcourse do some scripting but that's cumbersome. Is there a clean way in RC?

    Thanks

    Ankur

    • Post Points: 5
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Started by Ankur S at 13 Oct 2012 12:44 PM. Topic has 0 replies.