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 Hold violation at post P&R simulation 

Last post Sun, Oct 7 2012 11:28 PM by shahein. 0 replies.
Started by shahein 07 Oct 2012 11:28 PM. Topic has 0 replies and 9878 views
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  • Sun, Oct 7 2012 11:28 PM

    • shahein
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    • Joined on Mon, Feb 23 2009
    • Posts 4
    • Points 35
    Hold violation at post P&R simulation Reply

    Hello,

     I am working in a digital design. The functional, post synthesis and post P&R without IO pads are all working fine, i.e., functionally and with clean timing reports "no setup/hold violations". I just added the IO pads to the same design, I had to change the timing constraints a bit for the synthesis but I have a clean design at SOC Encounter, i.e., clean DRC and clean timing reports "no setup/hold violations". However, when I perform simulation using the exported net-list from SOC Encounter together with SDF exported from the same tool, I got a lot of hold violations. Consequently, the design is not funcitioning.

    Why and how I can overcome or trobleshoot this issue?

    In waiting for your feedback and comments.

    Regards.

    • Post Points: 5
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Started by shahein at 07 Oct 2012 11:28 PM. Topic has 0 replies.