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 Re: How to Simulate 64-bit VHDL Code in Cadence? 

Last post Wed, Sep 5 2012 6:16 AM by grasshopper. 0 replies.
Started by grasshopper 05 Sep 2012 06:16 AM. Topic has 0 replies and 833 views
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  • Wed, Sep 5 2012 6:16 AM

    • grasshopper
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    • Chelmsford, MA
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    Re: How to Simulate 64-bit VHDL Code in Cadence? Reply

     Hi shahein,

     this sounds like a VHDL issue and not a tool issue. Please refer to the VHDL LRM (IEEE1076) and refer to default types and precision. This will probably explain the behavior you are seeing and provide information on correct data types to use. Should you find any of the tools are not consistent with the LRM, please file a Service  Request so that it can be addressed

     

    thanks,

    gh-

    • Post Points: 5
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Started by grasshopper at 05 Sep 2012 06:16 AM. Topic has 0 replies.