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 How to Simulate 64-bit VHDL Code in Cadence? 

Last post Tue, Sep 4 2012 1:17 AM by shahein. 0 replies.
Started by shahein 04 Sep 2012 01:17 AM. Topic has 0 replies and 1063 views
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  • Tue, Sep 4 2012 1:17 AM

    • shahein
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    • Joined on Mon, Feb 23 2009
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    How to Simulate 64-bit VHDL Code in Cadence? Reply

    I am trying to simulate a VHDL code which have internally values exceeds the range of (-2**31 to 2**31). However, I can synthesize the code but I can't simulate it.

     I tried to change the attribute

     set intovf_severity_level IGNORE

    but it didn't work as well.

    I would appreciate your suggestions.

     Regards.

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    • Post Points: 5
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Started by shahein at 04 Sep 2012 01:17 AM. Topic has 0 replies.