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 Regarding the tie down diode 

Last post Tue, Jun 26 2012 7:37 PM by peterki. 2 replies.
Started by PeterXia 30 May 2012 01:35 PM. Topic has 2 replies.
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  • Wed, May 30 2012 1:35 PM

    • PeterXia
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    • Joined on Fri, May 18 2012
    • Posts 5
    • Points 70
    Regarding the tie down diode Reply

    Process: IBM analog/RF 130 nm.

     

    Hi all, tie down diodes are used to prevent gate damage during fabrication.

     

    For nMOS, it is clear that we can tie n+/sub diode to the gate, as a reverse biased diode.

     

    However, there is a pcell called pTiedown. It is p+ diffusion in n-well. What it is for?

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    • Post Points: 20
  • Tue, Jun 26 2012 5:45 PM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 944
    • Points 14,305
    Re: Regarding the tie down diode Reply

    Hi Peter

    The answer is in this designer's forum post. Would you happen to be "peterki" too? : )

    Best regards
    Quek

    • Post Points: 20
  • Tue, Jun 26 2012 7:37 PM

    • peterki
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    • Joined on Fri, Feb 24 2012
    • Posts 1
    • Points 5
    Re: Regarding the tie down diode Reply
    Hi Quek, Thank you so much for answering my question, as well as my other post. The answer to this post can be found at http://www.designers-guide.org/Forum/YaBB.pl?num=1338412194
    • Post Points: 5
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Started by PeterXia at 30 May 2012 01:35 PM. Topic has 2 replies.