Home > Community > Forums > Custom IC Design > Exporting Verilog netlist from Virtuoso Schematics

Share
  • Email
  • Social Web
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Exporting Verilog netlist from Virtuoso Schematics 

Last post Tue, Aug 31 2010 8:44 AM by Andrew Beckett. 1 replies.
Started by mingfatty 25 Aug 2010 09:11 PM. Topic has 1 replies.
Page 1 of 1 (2 items)
Sort Posts:

  • Wed, Aug 25 2010 9:11 PM

    • mingfatty
    • Top 500 Contributor
    • Joined on Tue, Mar 16 2010
    • Posts 23
    • Points 385
    Exporting Verilog netlist from Virtuoso Schematics Reply
    Hi Folks, I am using Virtuoso 5.1.41 to perform my simulation (delay, power and etc) and hoping to export the end design in Verilog form so that i ca use encounter to do the place and route for me. I could not find the option in the virtuoso and please kindly help on this issue. Many thanks in advance. Best regards, Ming Fatt
    • Post Points: 20

  • Tue, Aug 31 2010 8:44 AM

    Re: Exporting Verilog netlist from Virtuoso Schematics Reply

    Tools->Verilog Integration->NC Verilog (in the CIW).

    There's a similar menu under Tools from the schematic. 

    Regards,

    Andrew.

    • Post Points: 5
Page 1 of 1 (2 items)
Sort Posts:
Started by mingfatty at 25 Aug 2010 09:11 PM. Topic has 1 replies.