Hi, there
I am just on a mixed-signal project, sine we dont have
nc verilog licence, what can I do to simulate a mixed-signal project in
which both cadence schematic and Verilog HDL is used. When I asked the
digital guys, they told me they use vcs or vsim to compile the HDL
file. I wonder if it is possible for cadence to call other verilog
compilers?
Thanks.